Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
the third byte to the program counter if the specified bit tests true. The bit to be
tested and its condition (set or clear) is part of the opcode. The span of branching
is from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit of the
condition code register. Table 11-3 lists the jump and branch instructions.
Table 11-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
INSTRUCTION SET
MC68HC05P4A
Rev. 2.0
11-6
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
