Freescale Semiconductor, Inc.
CPU Core
Low-Power Modes
3.8.3 Da ta -Re te ntion Mod e
The contents of RAM and CPU registers are retained at supply voltages
as low as 2.0Vdc. This is called the data-retention mode where the data
is held, but the device is not guaranteed to operate. RESET must be held
low during data-retention mode.
Data Direction
Register Bit
Internal
HC05
I/O
Pin
Latched Output
Data Bit
Output
Connections
Input
Register
Bit
Input
I/O
Figure 3-3. Port I/O Circuitry
MC68HC05E1 — Revision 2.0
General Release Specification
CPU Core
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