Block Diagram
5.4 Block Diagram
any0
Priority
Level
Level 0
82->7
Priority
Encoder
7
2->4
INT1
Decode
INT
VAB
IPIC
CONTROL
any3
Level 3
Priority
Level
IACK
SR[9:8]
82->7
Priority
Encoder
7
PIC_EN
2->4
INT82
Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
Functional Mode
The ITCN is in this mode by default.
•
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA
and IRQB signals automatically become low-level sensitive in these modes even if the control register bits
are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling
edge.
A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop
mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA
and IRQB can wake it up.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
83
FREESCALE [ Freescale ]
