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56F8367_09 参数 Datasheet PDF下载

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型号: 56F8367_09
PDF下载: 下载PDF文件 查看货源
内容描述: 16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用: 控制器
文件页数/大小: 182 页 / 1852 K
品牌: FREESCALE [ Freescale ]
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Introduction  
Part 5 Interrupt Controller (ITCN)  
5.1 Introduction  
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to  
signal to the 56800E core when an interrupt of sufficient priority exists, and what address to jump in order  
to service this interrupt.  
5.2 Features  
The ITCN module design includes these distinctive features:  
Programmable priority levels for each IRQ  
Two programmable Fast Interrupts  
Notification to SIM module to restart clocks out of Wait and Stop modes  
Drives initial address on the address bus after reset  
For further information, see Table 4-5, Interrupt Vector Table Contents.  
5.3 Functional Description  
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 86 interrupt  
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of  
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the  
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number  
85 is the lowest.  
5.3.1  
Normal Interrupt Handling  
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest  
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the  
vector number to determine the vector address. In this way, an offset is generated into the vector table for  
each interrupt.  
5.3.2  
Interrupt Nesting  
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be  
serviced. The following tables define the nesting requirements for each priority level.  
Table 5-1 Interrupt Mask Bit Definition  
SR[9]1  
SR[8]1  
Permitted Exceptions  
Masked Exceptions  
None  
0
0
1
1
0
1
0
1
Priorities 0, 1, 2, 3  
Priorities 1, 2, 3  
Priorities 2, 3  
Priority 3  
Priority 0  
Priorities 0, 1  
Priorities 0, 1, 2  
1. Core status register bits indicating current interrupt mask within the core.  
56F8367 Technical Data, Rev. 9  
Freescale Semiconductor  
Preliminary  
81