5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00F1A0)
Register
Acronym
Base Address +
Register Name
Interrupt Priority Register 0
Section Location
IPR0
$0
$1
5.6.1
5.6.2
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Interrupt Priority Register 7
Interrupt Priority Register 8
Interrupt Priority Register 9
Vector Base Address Register
Fast Interrupt 0 Match Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High Register
Fast Interrupt 1 Match Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
IPR1
IPR2
$2
5.6.3
IPR3
$3
5.6.4
IPR4
$4
5.6.5
IPR5
$5
5.6.6
IPR6
$6
5.6.7
IPR7
$7
5.6.8
IPR8
$8
5.6.9
IPR9
$9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
VBA
$A
$B
$C
$D
$E
$F
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQP4
IRQP5
$10
$11
$12
$13
$14
$15
$16
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
Interrupt Control Register
ICTL
$1D
5.6.30
5.6.32
Reserved
IPR10
$1F
Interrupt Priority Register 10
Note: The IPR10 is NOT available in the 56F8167 device.
56F8367 Technical Data, Rev. 9
84
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
