Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
Address Offset
Register Description
Reserved
FCMB14_CONTROL
FCMB14_ID_HIGH
FCMB14_ID_LOW
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
$B0
$B1
$B2
$B3
$B4
$B5
$B6
Message Buffer 14 Control / Status Register
Message Buffer 14 ID High Register
Message Buffer 14 ID Low Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Reserved
FCMB15_CONTROL
FCMB15_ID_HIGH
FCMB15_ID_LOW
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
$B8
$B9
$BA
$BB
$BC
$BD
$BE
Message Buffer 15 Control / Status Register
Message Buffer 15 ID High Register
Message Buffer 15 ID Low Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Reserved
Table 4-39 FlexCAN2 Registers Address Map
(FC2_BASE = $00 FA00)
FlexCAN2 is NOT available in the 56F8167 device
Register Acronym
FC2MCR
Address Offset
Register Description
Module Configuration Register
$0
Reserved
FC2CTL0
$3
$4
$5
$6
$7
$8
$9
$A
$B
Control Register 0 Register
FC2CTL1
Control Register 1 Register
FC2TMR
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Interrupt Masks 2 Register
FC2MAXMB
FC2IMASK2
FC2RXGMASK_H
FC2RXGMASK_L
FC2RX14MASK_H
FC2RX14MASK_L
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
75
FREESCALE [ Freescale ]
