56F8367/56F8167 Features
Part 1 Overview
1.1 56F8367/56F8167 Features
1.1.1
Core
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Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1 outlines the key differences between the 56F8367 and 56F8167 devices.
Table 1-1 Device Differences
Feature
56F8367
56F8167
Guaranteed Speed
Program RAM
Data Flash
60MHz/60 MIPS
40MHZ/40MIPS
Not Available
Not Available
1 x 6
4KB
32KB
2 x 6
2
PWM
CAN
Not Available
2
Quad Timer
4
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
2 x 4
1
1 x 4
Not Available
7
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56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
5
FREESCALE [ Freescale ]
