Interrupt Vector Table
Table 4-4 Program Memory Map at Reset
Mode 11 (MA = 1)
Mode 0 (MA = 0)
Begin/End
Address
Internal Boot
External Boot
EMI_MODE = 02,3
EMI_MODE = 14
Internal Boot
16-Bit External Address Bus
16-Bit External Address Bus
20-Bit External Address Bus
External Program Memory6
P:$1F FFFF
P:$10 0000
External Program Memory5
External Program Memory5
P:$0F FFFF
P:$05 0000
P:$04 FFFF
P:$04 F800
On-Chip Program RAM
4KB
P:$04 F7FF
P:$04 4000
Reserved
92KB
P:$04 3FFF
P:$04 0000
Boot Flash
32KB
COP Reset Address = 04 0002
Boot Location = 04 0000
Boot Flash
32KB
(Not Used for Boot in this Mode)
External Program Memory
COP Reset Address = 04 00027
Boot Location = 04 00007
Internal Program Flash8
256KB
Internal Program Flash
256KB
P:$03 FFFF
P:$02 0000
P:$01 FFFF
P:$01 0000
Internal Program Flash
128KB
Internal Program Flash8
256KB
P:$00 FFFF
P:$00 0000
External Program Memory
COP Reset Address = 00 0002
Boot Location = 00 0000
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7.
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE = 0” when EMI_MODE pin is tied to ground at boot up.
4. “EMI_MODE = 1” when EMI_MODE pin is tied to V at boot up.
DD
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
6. Not accessible in reset configuration, since the address is above P:$0F FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
7. Booting from this external address allows prototyping of the internal Boot Flash.
8. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must
have its own mass erase.
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
43
FREESCALE [ Freescale ]
