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56F8367_09 参数 Datasheet PDF下载

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型号: 56F8367_09
PDF下载: 下载PDF文件 查看货源
内容描述: 16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用: 控制器
文件页数/大小: 182 页 / 1852 K
品牌: FREESCALE [ Freescale ]
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The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part  
5.6.11 for the reset value of the VBA.  
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the  
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or  
JMP instructions. All other entries must contain JSR instructions.  
Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the  
56F8167 device.  
1
Table 4-5 Interrupt Vector Table Contents  
Vector  
Number  
Priority  
Level  
Vector Base  
Address +  
Peripheral  
Interrupt Function  
Reserved for Reset Overlay2  
Reserved for COP Reset Overlay2  
Illegal Instruction  
core  
2
3
4
5
6
7
3
3
P:$04  
P:$06  
P:$08  
P:$0A  
P:$0C  
P:$0E  
core  
core  
core  
core  
core  
SW Interrupt 3  
3
HW Stack Overflow  
Misaligned Long Word Access  
OnCE Step Counter  
OnCE Breakpoint Unit 0  
Reserved  
3
1-3  
1-3  
core  
core  
core  
9
1-3  
1-3  
1-3  
P:$12  
P:$14  
P:$16  
OnCE Trace Buffer  
OnCE Transmit Register Empty  
OnCE Receive Register Full  
Reserved  
10  
11  
core  
core  
core  
core  
core  
14  
15  
16  
17  
18  
2
1
P:$1C  
P:$1E  
P:$20  
P:$22  
P:$24  
SW Interrupt 2  
SW Interrupt 1  
0
SW Interrupt 0  
0-2  
0-2  
IRQA  
IRQB  
Reserved  
LVI  
PLL  
FM  
FM  
FM  
20  
21  
22  
23  
24  
0-2  
0-2  
0-2  
0-2  
0-2  
P:$28  
P:$2A  
P:$2C  
P:$2E  
P:$30  
Low-Voltage Detector (power sense)  
PLL  
FM Access Error Interrupt  
FM Command Complete  
FM Command, data and address Buffers Empty  
Reserved  
56F8367 Technical Data, Rev. 9  
44  
Freescale Semiconductor  
Preliminary  
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