1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-20 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-21 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-22 TRST Timing Diagram
56F8367 Technical Data, Rev. 9
160
Freescale Semiconductor
Preliminary