GPIOD_PER Register
GPIO Controlled
0
1
I/O Pad Control
SIM_ GPS Register
0
1
EMI Controlled
CAN2 Controlled
Figure 6-11 Overall Control of GPIOD Pads Using SIM_GPS Control
1
Table 6-3 Control of GPIOD Pads Using SIM_GPS Control
Control Registers
Pin Function
Comments
GPIO Input
0
0
1
1
0
1
—
—
0
GPIO Output
EMI I/O
—
—
EMI CSn pins are always outputs
CAN2
1
CAN2_TX is always an output
CAN2_RX is always an input
1. This applies to the two pins that serve as EMI CSn / CAN2 / GPIOD functions. A separate set of control bits is used for
each pin.
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
D1
0
4
D0
0
3
C3
0
2
C2
0
1
C1
0
0
C0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
Figure 6-12 GPIO Peripheral Select Register (SIM_GPS)
Reserved—Bits 15–6
6.5.8.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8367 Technical Data, Rev. 9
122
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
