5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.30.5 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3
This read-only bit reflects the state of the external IRQB pin.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1
This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQB interrupt is a low-level sensitive (default)
1 = IRQB interrupt is falling-edge sensitive
5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
•
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive
5.6.31 Reserved—Base + $1E
5.6.32 Interrupt Priority Register 10 (IPR10)
Base + $1F
Read
15
0
14
0
13
0
12 11 10
9
0
8
0
7
6
5
4
3
2
1
0
0
0
0
FLEXCAN2_
MSGBUF IPL
FLEXCAN2_
WKUP IPL
FLEXCAN2_
BOFF IPL
FLEXCAN2_
ERR IPL
Write
RESET
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Note: This register is NOT available in the 56F8167 device.
56F8367 Technical Data, Rev. 9
108
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
