Register Descriptions
5.6.23.2 IRQ Pending (PENDING)—Bits 81–85
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 85.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.24 Reserved—Base + 17
5.6.25 Reserved—Base + 18
5.6.26 Reserved—Base + 19
5.6.27 Reserved—Base + 1A
5.6.28 Reserved—Base + 1B
5.6.29 Reserved—Base + 1C
5.6.30 ITCN Control Register (ICTL)
Base + $1D
Read
15
14
13
12 11 10
9
8
7
6
0
5
INT_DIS
0
4
1
3
2
1
0
INT
IPIC
VAB
IRQB STATE IRQA STATE
IRQB IRQA
EDG
EDG
Write
0
0
0
1
0
0
0
0
0
1
1
1
0
0
RESET
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
•
•
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
•
•
•
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
107
FREESCALE [ Freescale ]
