5.6.21 IRQ Pending 3 Register (IRQP3)
Base + $14
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [64:49]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1 IRQ Pending (PENDING)—Bits 64–49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.22 IRQ Pending 4 Register (IRQP4)
Base + $15
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING [80:65]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1 IRQ Pending (PENDING)—Bits 80–65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.23 IRQ Pending 5 Register (IRQP5)
Base + $16
Read
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0
1
PENDING[85:81]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1 Reserved—Bits 96–86
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.
56F8367 Technical Data, Rev. 9
106
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
