Power Consumption
Table 10-24 IO Loading Coefficients at 10MHz
Intercept
Slope
PDU08DGZ_ME
PDU04DGZ_ME
1.3
0.11mW / pF
0.11mW / pF
1.15mW
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-24 provides coefficients for calculating power dissipated
in the IO cells as a function of capacitive load. In these cases:
Total Power = Σ((Intercept +Slope*Cload)*frequency/10MHz)
where:
•
•
•
Summation is performed over all output pins with capacitive loads
Total Power is expressed in mW
Cload is expressed in pF
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
2
device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V =
0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs
driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
157
FREESCALE [ Freescale ]
