Serial Peripheral Interface (SPI) Timing
1
Table 10-17 SPI Timing (Continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Data invalid
Master
Slave
tDI
10-9, 10-10,
0
0
—
—
ns
ns
10-11
Rise time
Master
Slave
tR
10-9, 10-10,
10-11, 10-12
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
tF
10-9, 10-10,
10-11, 10-12
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
tDV
MOSI
(Output)
Master MSB out
tF
Bits 14–1
Master LSB out
tR
Figure 10-9 SPI Master Timing (CPHA = 0)
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
145
FREESCALE [ Freescale ]
