Reset, Stop, Wait, Mode Select, and Interrupt Timing
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET
tRA
tRAZ
tRDA
A0–A15,
D0–D15
First Fetch
Figure 10-4 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 10-5 External Interrupt Timing (Negative Edge-Sensitive)
A0–A15
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 10-6 External Level-Sensitive Interrupt Timing
IRQA,
IRQB
tIRI
A0–A15
First Interrupt Vector
Instruction Fetch
Figure 10-7 Interrupt from Wait State Timing
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
143
FREESCALE [ Freescale ]
