tIW
IRQA
tIF
A0–A15
First Instruction Fetch
Not IRQA Interrupt Vector
Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing
10.9 Serial Peripheral Interface (SPI) Timing
1
Table 10-17 SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
10-9, 10-10,
10-11, 10-12
50
50
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
10-12
10-12
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCK) high time
Master
Slave
10-9, 10-10,
10-11, 10-12
17.6
25
—
—
ns
ns
Clock (SCK) low time
Master
Slave
10-12
24.1
25
—
—
ns
ns
Data set up time required for inputs
Master
Slave
tDS
tDH
tA
10-9, 10-10,
10-11, 10-12
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
10-9, 10-10,
10-11, 10-12
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
10-12
10-12
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
10-9, 10-10,
10-11, 10-12
—
—
4.5
20.4
ns
ns
56F8345 Technical Data, Rev. 17
144
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
