External Bus Asynchronous Timing
3.5 External Bus Asynchronous Timing
1,2
Table 3-10 External Bus Asynchronous Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Unit
Min
Max
Address Valid to WR Asserted
tAWR
tWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
7.5
(T*WS)+7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
tWRD
tDOH
tDOS
—
T + 4.2
—
ns
ns
Data Out Hold Time from WR Deasserted
4.8
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
2.2
(T*WS)+6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
tRDA
0
—
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
ns
ns
Input Data Hold to RD Deasserted
tDRD
tRD
0
—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
19
—
—
ns
ns
(T*WS)+19
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
—
—
1
ns
ns
(T*WS)+1
Address Valid to RD Asserted
tARDA
tRDD
-4.4
—
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
—
—
2.4
ns
ns
(T*WS) + 2.4
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
tWRRD
tRDRD
tWRWR
tRDWR
6.8
0
—
—
—
—
ns
ns
ns
ns
14.1
12.8
56F807 Technical Data Technical Data, Rev. 16
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