56F8036 General Description
• Up to 32 MIPS at 32MHz core frequency
• One Queued Serial Peripheral Interface (QSPI)
• DSP and MCU functionality in a unified,
C-efficient architecture
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• 64KB (32K x 16) Program Flash
• One 16-bit Quad Timer clocked at up to 96MHz
2
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module clocked at up to 96MHz
• One Inter-Integrated Circuit (I C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Two independent 5-channel 12-bit high-speed
Analog-to-Digital Converters (ADCs)
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• Two internal 12-bit Digital-to-Analog Converters
(DACs)
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• Up to 39 GPIO lines
• 48-pin LQFP Package
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
RESET or
GPIOA
V
2
V
2
V
V
V
SSA
CAP
DD
SS
DDA
4
3
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Low-Voltage
Supervisor
Analog Reg
PWM
or TMRA or CMP
or GPIOA
11
16-Bit
56800E Core
Data ALU
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Bit
Manipulation
Unit
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
PAB
PDB
CDBR
CDBW
DAC
AD0
5
5
Memory
R/W Control
ADC
or CMP
XDB2
XAB1
XAB2
Program Memory
32K x 16 Flash
or GPIOC
System Bus
Control
AD1
PAB
Unified Data /
Program RAM
4K x 16
PDB
CDBR
CDBW
Programmable
Interval
Timer
IPBus Bridge (IPBB)
QSCI
QSPI
2
or PWM
I C
or PWM
2
or CAN
or CMP
or GPIOB
or I C
2
or I C
XTAL, CLKIN, or
GPIOD
P
or TMRA
or GPIOB
System
Integration
Module
or TMRA
or GPIOB
Interrupt
Controller
COP/
Watchdog
O
O
S
C
Clock
Generator*
R
EXTAL or GPIOD
*Includes On-Chip
Relaxation Oscillator
4
4
3
56F8036 Block Diagram
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
3
FREESCALE [ Freescale ]
