Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
User Status Register
Command Register
Data Buffer Register
USTAT
CMD
FMUSTAT
FMCMD
FMDATA
FMOPT1
FM_USTAT
FM_CMD
FM_DATA
FM_OPT1
FMUSTAT
FMCMD
FMUSTAT
FMCMD
FMDATA
FMOPT1
0xF413
0xF414
0xF418
0xF41B
DATA
OPT1
FMDATA
FMOPT1
Info Optional Data 1
Register
Test Array Signature
Register
TSTSIG
FMTST_SIG
FM_TSTSIG
FMTST_SIG
FMTST_SIG
0xF41D
General Purpose Input/Output (GPIO) Module
x= A (n=0) B (n=1) C (n=2) D (n=3)
Pull-Up Enable
Register
PUPEN
PUR
GPIOx_PUPEN
GPIOx_PUR
GPIO_x_PUR
0xF1n0
Data Register
DATA
DDIR
DR
GPIOx_DATA
GPIOx_DDIR
GPIOx_DR
GPIO_x_DR
0xF1n1
0xF1n2
Data Direction
Register
DDR
GPIOx_DDR
GPIO_x_DDR
Peripheral Enable
Register
PEREN
IASSRT
IEN
PER
IAR
GPIOx_PEREN
GPIOx_IASSRT
GPIOx_IEN
GPIOx_PER
GPIOx_IAR
GPIO_x_PER
GPIO_x_IAR
0xF1n3
0xF1n4
0xF1n5
0xF1n6
0xF1n7
0xF1n8
Interrupt Assert
Register
Interrupt Enable
Register
IENR
IPOLR
IPR
GPIOx_IENR
GPIOx_IPOLR
GPIOx_IPR
GPIO_x_IENR
GPIO_x_IPOLR
GPIO_x_IPR
Interrupt Polarity
Register
IPOL
GPIOx_IPOL
Interrupt Pending
Register
IPEND
IEDGE
GPIOx_IPEND
GPIOx_IEDGE
Interrupt
IESR
GPIOx_IESR
GPIO_x_IESR
Edge-Sensitive
Register
Push-Pull Mode
Registers
PPOUTM
RDATA
DRIVE
PPMODE
RAWDATA
DRIVE
GPIOx_PPOUTM
GPIOx_RDATA
GPIOx_DRIVE
GPIOx_PPMODE
GPIOx_RAWDATA
GPIOx_DRIVE
GPIO_x_PPMODE
GPIO_x_RAWDATA
GPIO_x_DRIVE
0xF1n9
0xF1nA
0xF1nB
Raw Data Input
Register
Output Drive Strength
Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
157
FREESCALE [ Freescale ]
