Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
Inter-Integrated Circuit Interface (I2C) Module
Control Register
CTRL
TAR
IBCR
I2C_CTRL
I2C_TAR
I2C_IBCR
I2CTAR
I2C_IBCR
I2C_TAR
0xF280
0xF282
Target Address
Register
Slave Address
Register
SAR
DATA
I2C_SAR
I2C_DATA
I2CSAR
I2C_SAR
0xF242
0xF288
0xF28A
Data Buffer &
Command Register
I2C_DATACMD
I2C_SS_SCLHCNT
I2C_DATACMD
I2C_SS_SCLHCNT
Standard Speed
Clock SCL High
Count Register
SSHCNT
I2C_SS_SCL_HCNT
Standard Speed
Clock SCL Low Count
Register
SSLCNT
FSHCNT
FSLCNT
I2C_SS_SCL_LCNT
I2C_FS_SCL_HCNT
I2C_FS_SCL_LCNT
I2C_SS_SCLLCNT
I2C_FS_SCLHCNT
I2C_FS_SCLLCNT
I2C_SS_SCLLCNT
I2C_FS_SCLHCNT
I2C_FS_SCLLCNT
0xF28C
0xF28E
0xF290
Fast Speed Clock
SCL High Count
Register
Fast Speed Clock
SCL Low Count
Register
Interrupt Status
Register
ISTAT
IENBL
RISTAT
RXFT
I2C_INTR_STAT
I2C_INTR_MASK
I2C_INTRSTAT
I2C_INTRMASK
I2C_INTRSTAT
I2C_INTRMASK
I2C_RAW_INTRSTAT
I2C_RXTL
0xF296
0xF298
0xF29A
0xF29C
Interrupt Mask
Register
Raw Interrupt Status
Register
I2C_RAW_INTR_ STAT I2C_RAW_INTRSTAT
I2C_RXTL
Receive FIFO
Threshold Level
Register
Transmit FIFO
Threshold Level
Register
TXFT
I2C_TXTL
I2C_TXTL
0xF29E
0xF2A0
Clear Combined &
Individual Interrupts
Register
CLRINT
I2C_CLRINTR
I2C_CLRINTR
Clear Receive Under
Interrupt Register
CLRRXUND
CLRRXOVR
CLRTXOVR
CLRRDREQ
CLRTXABRT
CLRRXDONE
I2C_CLR_RXUNDER
I2C_CLROVER
I2C_CLR_RXUNDER
I2C_CLROVER
0xF2A2
0xF2A4
0xF2A6
0xF2A8
0xF2AA
0xF2AC
Clear Receive Over
Interrupt Register
Clear Transmit Over
Register
I2C_CLR_TXOVER
I2C_CLR_RDREQ
I2C_CLR_TXABRT
I2C_CLR_RXDONE
I2C_CLR_TXOVER
I2C_CLR_RDREQ
I2C_CLR_TXABRT
I2C_CLR_RXDONE
Clear Read Required
Interrupt Register
Clear Transmit Abort
Interrupt Register
Clear Receive Done
Interrupt Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
155
FREESCALE [ Freescale ]
