Add.
Offset
Register Acronym
GPIOC_PUPEN
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
R
W
PU
D
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
X
0
1
0
0
1
0
0
0
0
0
1
X
0
1
0
0
1
0
0
0
0
0
1
X
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
X
0
1
0
0
1
0
0
0
0
0
1
X
0
1
R
W
GPIOC_DATA
GPIOC_DDIR
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
X
0
R
W
DD
PE
IA
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
GPIOC_PEREN
GPIOC_IASSRT
GPIOC_IEN
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IEN
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IEPOL
GPIOC_IEPOL
GPIOC_IPEND
GPIOC_IEDGE
GPIOC_PPOUTM
GPIOC_RDATA
GPIOC_DRIVE
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IPR
IES
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
R
W
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
OEN
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
RAW DATA
RS
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
R
W
DRIVE
RS
0
0
0
0
0
0
0
0
0
0
0
R
W
Read as 0
Reserved
Reset
RS
Figure 8-3 GPIOC Register Map Summary
56F8014 Technical Data, Rev. 9
88
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
