Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8014 are organized into functional groups, as detailed in
Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or
signals present on a pin, sorted by pin number.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (VDD or VDDA
)
2
3
Ground (VSS or VSSA
)
Supply Capacitors
Reset
1
1
5
Pulse Width Modulator (PWM) Ports1
Serial Peripheral Interface (SPI) Ports2
Analog-to-Digital Converter (ADC) Ports
4
8
2
Timer Module Ports3
Serial Communications Interface (SCI) Ports4
2
4
JTAG/Enhanced On-Chip Emulation (EOnCE)
1. Pins in this section can function as TMR and GPIO.
2
2. Pins in this section can function as TMR, I C, and GPIO.
3. Pins can function as PWM and GPIO.
2
4. Pins in this section can function as I C and GPIO.
56F8014 Technical Data, Rev. 9
14
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
