(Continued from Figure 1-2)
To/From IPBus Bridge
PWM0 - 3
4
PWM0 - 3
2
PWM4, 5
Fault1, 2
Fault0
GPIOA0 - 3
PWM
2
PWM4, 5
Fault1, 2
T2, 3
Output Controls
Fault3
GPIOA4 - 5
GPIOA6
Reload
Pulse
2
3
2
Fault0
Fault3
from ADC
2
T3i
T2/3
T1
T1
GPIOB5
GPIOB4
Timer
T0
T2o, T3o
T0
I2C is muxed with both SPI and SCI.
T2 and T3 are muxed with SPI and PWM.
CLKO
2
2
TXD, RXD
SDA, SCL
2
2
SCI
I2C
GPIOB6 - 7
GPIOB0 - 1
GPIOB2 - 3
SCLK, SS
2
2
SPI
MISO, MOSI
T2, 3
3
to PWM
3
Sync0,
Sync1
ANA0, 1, 3
ANA2
Over/Under
Limits
ANA0, 1, 3
ANA2
ANB2
GPIOC0, 1, 3
VREFH, VREFL
ADC
ANB2
V
REFH, VREFL
2
3
ANB0, 1, 3
GPIOC2, 6
ANB0, 1, 3
GPIOC4, 5, 7
IPBus
Figure 1-3 56F8014 Peripheral I/O Pin-Out
56F8014 Technical Data, Rev. 9
12
Freescale Semiconductor
Preliminary