FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
OPTION
MSB
LSB
GRPC/E ENABLED
GRPC/E DISABLED
2
0
1
REG5 ramps up first
REG5, REG6 and REG7 ramp down together
Then REG6 and REG7 ramp up together
3
4
1
1
0
1
REG5, REG6, and REG7 ramp up together
REG5, REG6, and REG7 ramp down together
REG5 and REG6 ramp up together first.
Then ramp up REG7
REG7 ramps down first.
Then REG5 and REG6 ramp down together
Switching frequency for REG6, 7 & 8
can decide whether to shutdown the output or not. In the
mean time, the concerned output control loop will be
attempting to correct the error.
FSW2 can be selected to be between 250 kHz and 1.0 MHz
in 250 kHz steps. On the 34704B, FSW2 is just for REG8
since REG6 and 7 do not exist in this device.
See Output Over-voltage/Under-voltage Monitoring on
page 30 for more details.
34704 assigns 2 bits to program FSW2 (FSW2 [1:0])
Response A and Response B share the same flag bit
34704 assigns 1 bit for this function (OVUVSETx) where x
corresponds to each regulator.
FSW2
500kHz (Default)
250kHz
MSB
LSB
0
0
0
1
1
1
OV/UV Response
bit
0
750kHz
0
A (Default)
B
1000kHz
1
1
Shutdown Hold (Delay) Time
The 34704 assigns 2 bits (SDDELAY[1:0]) for the
Dynamic Voltage Scaling for each regulator
processor to program the shutdown delay time period
The customer can adjust each regulator’s output
dynamically with 2.5% step size. The total range of
adjustability will vary depending on each regulator to
accommodate different operating environments. Some
regulators will utilize the full range of -20.00% to +17.50%
and some regulators will only use the range of ±10.00%. For
details, see each regulator’s section. Each 2.5% step takes
50 μs before moving to the next step. REG8 only performs
DVS when in voltage regulation mode.
Shutdown Delay
1.0sec (Default)
0.5sec
MSB
LSB
0
0
0
1
1
1
1.5sec
0
2.0sec
1
Please refer to the /ONOFF pin description for more
details
During DVS, the Over-voltage and Under-voltage
monitoring will not be active. In addition to that, these faults
will be masked and not active for a DVS settling time period
equal to 1ms. This DVS settling time will start after the
DVSSTAT register is flagged indicating that the DVS cycle is
done. This is to ensure that during DVS and soft start alike
the output will not be tripped due to a momentary over-
voltage or under-voltage fault. This is the same for Response
A and Response B of the over-voltage/under-voltage fault
monitoring.
Programming 34704 response to under-voltage/over-
voltage conditions on each regulator
There are two responses that can be programmed for an
over-voltage/under-voltage condition:
Response A: When an over-voltage (under-voltage) event
is detected, the concerned output shuts down and a register
is flagged to alert the processor.
34704 assigns 4 bits register to program the Dynamic
Voltage Scaling for each regulator (DVSSETx[3:0]) where x
corresponds to each regulator.
Response B: When an over-voltage/under-voltage event
is detected, the concerned output will not shutdown, but the
register is flagged to alert the processor. Then, the processor
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
FREESCALE [ Freescale ]
