FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Address 1110—Under-voltage/Over-voltage Register
(UOVR)
A valid message length is determined following a CS
transition of Logic [0] to Logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A
valid message length is a multiple of eight bits. At this time,
the SO pin is tri-stated and the fault status register is now
able to accept new fault status information.
The UOVR register can be used to disable or enable the
over-voltage and/or under-voltage protection. By default ([0]),
both protections are active. When disabled, an under-voltage
or over-voltage condition fault will not be reported in bits D1
and D0 of the output fault register.
The output status register correctly reflects the status of
the STATR-selected register data at the time the CS is pulled
to a Logic [0] during SPI communication and/or for the period
of time since the last valid SPI communication, with the
following exceptions:
Address x111—TEST
The TEST register is reserved for test and is not
accessible with SPI during normal operation.
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output status register is
loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI pin. The first
eight bits of data clocking out of the SO, and following a CS
transition, are dependant upon the previously written SPI
word.
communication following an under-voltage VPWR
condition should be ignored.
• The RST pin transition from a Logic [0] to Logic [1] while
the WAKE pin is at Logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
Any bits clocked out of the SO pin after the first eight will
be representative of the initial message bits clocked into the
SI pin since the CS pin first transitioned to a Logic [0]. This
feature is useful for daisy chaining devices as well as
message verification.
Table 16. Serial Output Bit Map Descriptions
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
WDin
WDin
WDin
WDin
WDin
0
OD6
OD5
OD4
OD3
OD2
UVF
OD1
OVF
OD0
FAULT
IN_SPI
SOCL0
OCLT0
A/O
x
x
x
x
x
0
1
0
1
x
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
OTF
0
OCHF
OCLF
OLF
0
1
1
0
0
0
1
1
–
1
0
1
0
1
1
0
0
–
0
SOCH
OL_dis
Fast SR
FSM_HS
0
0
CSNS EN
SOCL1
OCLT1
IN dis
OSD1
WD1
0
SOCL2
CD_dis
CSNS high
OSD2
WDTO
IN Pin
1110
0
1
1
OSD0
WD0
1
1
0
1
0
FSI Pin
UV_dis
–
WAKE Pin
OV_dis
–
1
1
0
WDin
–
See Table 1
–
x = Don’t care.
Previous Address SOA[2:0]=000
SERIAL OUTPUT BIT ASSIGNMENT
The eight bits of serial output data depend on the previous
serial input message, as explained in the following
If the previous three MSBs are 000, bits OD6:OD0 reflect
the current state of the Fault register (FLTR) (Table 17).
paragraphs. Table 16 summarizes the SO register content.
Previous Address SOA[2:0]=001
Bit OD7 reflects the state of the watchdog bit (D7)
addressed during the prior communication. The contents of
bits OD6:OD0 depend upon the bits D2:D0 from the most
recent STATR command SOA2:SOA0.
The data in bits OD1 and OD0 contain CSNS EN and
IN_SPI programmed bits, respectively.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
FREESCALE [ Freescale ]
