FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
eight possible levels as defined in Table 11. Bit D3 is used to
set the over-current high detection level to one of two levels
as defined in Table 12.
Table 10. Serial Input Address and Configuration Bit
Map
Serial Input Data
SI
Table 11. Over-current Low Detection Levels
Register
D7 D6 D5 D4
D3
0
D2
SOA2
0
D1
D0
SOCL2 SOCL1 SOCL0
Over-current Low Detection
(Amperes)
STATR
OCR
x
x
0
0
0
0
0
1
SOA1
SOA0
(D2)
(D1)
(D0)
0
CSNS IN_SPI
EN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
45
40
35
30
25
20
15
SOCHLR
CDTOLR
DICR
x
x
x
0
0
1
1
1
0
0
1
0
SOCH SOCL2 SOCL1 SOCL0
OL_dis CD_dis OCLT1 OCLT0
FAST CSNS
IN dis
A/O
SR
high
OSDR
WDR
NAR
0
1
0
1
x
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
OSD2
OSD1
WD1
0
OSD0
WD0
0
0
0
0
0
0
UOVR
TEST
0
UV_dis OV_dis
Table 12. Over-current High Detection Levels
Freescale Internal Use (Test)
Over-current High Detection
x = Don’t care.
SOCH (D3)
(Amperes)
DEVICE REGISTER ADDRESSING
0
1
150
100
The following section describes the possible register
addresses and their impact on device operation.
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
Address x000—Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2, D1, and D0 determine the content of the first eight bits of
SO data. In addition to the device status, this feature provides
the ability to read the content of the OCR, SOCHLR,
CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers.
(Refer to the section entitled Serial Output Communication
(Device Status Return Data) beginning on page 26.)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before output latches OFF occurs. Bits D1 and D0
allow the MCU to select one of four fault blanking times
defined in Table 13. Note that these timeouts apply only to
the over-current low detection levels. If the selected over-
current high level is reached, the device will latch off within
20 μs.
Table 13. Over-current Low Detection Blanking Time
Address x001—Output Control Register (OCR)
OCLT[1:0]
Timing
The OCR register allows the MCU to control the output
through the SPI. Incoming message bit D0 (IN_SPI) reflects
the desired states of the high-side output: a Logic [1] enables
the output switch and a Logic [0] turns it OFF. A Logic [1] on
message bit D1 enables the Current Sense (CSNS) pin. Bits
D2 and D3 must be Logic [0]. Bit D7 is used to feed the
watchdog if enabled.
00
01
10
11
155 ms
10 ms
1.2 ms
150 μs
A Logic [1] on bit D2 disables the over-current low
(CD_dis) detection timeout feature. A Logic [1] on bit D3
disables the open load (OL) detection feature.
Address x010—Select Over-current High and Low
Register (SOCHLR)
The SOCHLR register allows the MCU to configure the
output over-current low and high detection levels,
Address x100—Direct Input Control Register (DICR)
respectively. In addition to protecting the device, this slow
blow fuse emulation feature can be used to optimize the load
requirements to match system characteristics. Bits D2:D0
are used to set the over-current low detection level to one of
The DICR register is used by the MCU to enable, disable,
or configure the direct IN pin control of the output. A Logic [0]
on bit D1 will enable the output for direct control by the IN pin.
A Logic [1] on bit D1 will disable the output from direct control.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FREESCALE [ Freescale ]
