ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ≤ VPWR = VSUP ≤ 40 V, -40°C ≤ TA ≤ 135°C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
GATE DRIVE (CONTINUED)
Duty Cycle (43), (44)
tDC
tDC
0.0
–
–
–
96
%
s
100% Duty Cycle Duration (43), (44)
Maximum Programmable Deadtime (45)
OVER-CURRENT COMPARATOR
Over-current Protection Filter Time
Unlimited
19.6
tMAX
10.2
15
µs
tOC
0.9
10
–
–
3.5
µs
ns
Rise Time (OC_OUT)
10% - 90%
tROC
240
CL = 100 pF
Fall Time (OC_OUT)
90% - 10%
tFOC
10
–
200
ns
CL = 100 pF
DESATURATION DETECTOR AND PHASE COMPARATOR
Phase Comparator Propagation Delay Time to 50% of VDD; CL ≤ 100 pF
ns
ns
Rising Edge Delay
Falling Edge Delay
tR
tF
–
–
–
–
200
350
Phase Comparator Match (Prop Delay Mismatch of Three Phases)
CL = 100 pF (43)
tMATCH
–
–
100
Desaturation and Phase Error Blanking Time(46)
tBLANK
tFILT
4.7
7.1
9.1
µs
ns
Desaturation Filter Time (Filter Time is digital) (43)
Fault Must be Present for This Time to Trigger
640
937
1231
CURRENT SENSE AMPLIFIER
Output Settle Time to 99% (43), (47)
tSETTLE
µs
RL = 1.0 kΩ, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5 to 15
–
1.0
2.0
Notes
43. This parameter is guaranteed by design, not production tested.
44. Maximum duty cycle is actually 100% because there is an internal charge pump to maintain the gate voltage in the 100% on condition.
However, in high duty cycle cases, there may not be sufficient time to recharge the bootstrap capacitors during the off time. Large
bootstrap capacitors will allow high duty cycles to be obtained for a short time. For applications needing closer to 100% duty cycle,
external diodes may optionally be used to provide high peak current charging capability to the bootstrap capacitors. These diodes would
be connected between VLS and the Px_BOOTSTRAP pins. In applications with lower gate charge requirements, the maximum duty
cycle can also be increased.
45. A Minimum Deadtime of 0.0 can be set via an SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock
cycle duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this
value limits at this value.
46. Blanking time, tBLANK, is applied to all phases simultaneously when switching ON any output FET. This precludes false errors due to
system noise during the switching event.
47. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
33937
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FREESCALE [ Freescale ]
