FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Interrupt Mask Register - IMR
LINM - LIN Interrupts Mask
This register allows masking of some of the interrupt
sources. The respective flags within the Interrupt Source
Register (ISR) will continue to work but will not generate
interrupts to the MCU. The 5V Regulator over-temperature
prewarning interrupt and Under-Voltage (VSUV) interrupts
can not be masked and will always cause an interrupt.
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
Writing to the IMR will return the ISR.
This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the VSUP over-voltage interrupt.
Table 28. Interrupt Mask Register - $E
C3
C2
C1
C0
1 = Interrupts Enabled
0 = Interrupts Disabled
Write
HSM
LSM
LINM
VMM
Reset
Value
Interrupt Source Register - ISR
1
1
1
1
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
Reset
Condition
POR
HSM - High Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the high side block.
This register is also returned when writing to the Interrupt
Mask Register (IMR).
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
Table 29. Interrupt Source Register - $E/$F
LSM - Low Side Interrupt Mask
S3
S2
S1
S0
This write-only bit enables/disables interrupts generated in
the low side block.
Read
ISR3
ISR2
ISR1
ISR0
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
ISRx - Interrupt Source Register
These read-only bits indicate the interrupt source following
Table 30. If no interrupt is pending then all bits are 0.
In case more than one interrupt is pending, the interrupt
sources are handled sequentially multiplex.
Table 30. Interrupt Sources
Interrupt Source
Priority
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
no interrupt
no interrupt
none
Lx Wake-up from Stop Mode-
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
highest
-
-
LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN
OC) or LIN Wake-up
0
0
1
1
0
1
1
0
Voltage Monitor Interrupt
Voltage Monitor Interrupt
(High Voltage)
(Low Voltage and VDD over-temperature)
-
Forced Wake-up
lowest
33912
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
FREESCALE [ Freescale ]
