FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Timing Control Register - TIMCR
This option is only active if one of the high side switches is
enabled when entering in Stop or Sleep Mode. Otherwise a
timed wake-up is performed after the period shown in
Table 23.
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
Table 23. Cyclic Sense Interval
CYSX8(60) CYST2
CYST1
CYST0
Interval
Table 21. Timing Control Register - $A
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No cyclic sense
20ms
C3
C2
C1
C0
0
WD2
WD1
WD0
0
40ms
Write
CS/WD
CYST2
CYST1
CYST0
0
60ms
0
80ms
Reset
Value
-
-
0
0
0
0
100ms
120ms
140ms
160ms
320ms
480ms
640ms
800ms
960ms
1120ms
0
Reset
Condition
POR
0
1
CS/WD - Cyclic Sense or Watchdog prescaler select
1
This write-only bit selects which prescaler is being written
to, the Cyclic Sense prescaler or the Watchdog prescaler.
1
1
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
1
1
1
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 22. This configuration is valid only if
windowing watchdog is active.
Notes
60. bit CYSX8 is located in Configuration Register (CFR)
Watchdog Status Register - WDSR
This register returns the Watchdog status information and
is also returned when writing to the TIMCR.
Table 22. watchdog Prescaler
WD2
WD1
WD0
Prescaler Divider
Table 24. Watchdog Status Register - $A/$B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
S3
S2
S1
S0
4
Read
WDTO
WDERR WDOFF
WDWO
6
8
WDTO - Watchdog Timeout
10
12
14
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
Any access to this register or the Timing Control Register
(TIMCR) will clear the WDTO bit.
CYSTx - Cyclic Sense Period Prescaler Select
1 = Last reset caused by watchdog timeout
0 = None
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 41).
33912
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
FREESCALE [ Freescale ]
