FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to
the section entitled Serial Output Communication (Device
Status Return Data) beginning on page 24.)
Table 11. Over-current Low Detection Levels
Over-current Low
SOCL2_s* SOCL1_s* SOCL0_s*
Detection (Amperes)
(D2)
(D1)
(D0)
ADDRESS 00001—OUTPUT CONTROL REGISTER
HS0 to HS3
(OCR0)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
8.9
7.9
7.0
5.8
4.8
3.9
2.8
The OCR0 register allows the MCU to control the ON/OFF
state of four outputs through the SPI. Incoming message bit
D3:D0 reflects the desired states of the four high side outputs
(INx_SPI), respectively. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001—OUTPUT CONTROL REGISTER
(OCR1)
Incoming message bits D3:D0 reflect the desired output
that will be mirrored on the Current Sense (CSNS) pin. A
logic [1] on message bits D3:D0 enables the CSNS pin for
outputs HS3:HS0, respectively. In the event the current
sense is enabled for multiple outputs, the current will be
summed. In the event that bits D3:D0 are all logic [0], the
output CSNS will be tri-stated. This is useful when several
CSNS pins of several devices share the same A/D converter.
* “_s” refers to the output, which is selected through bits D12:D11;
refer to Table 10, page 23.
Table 12. Over-current High Detection Levels
Over-current High Detection (Amperes)
SOCH_s* (D3)
HS0 to HS3
ADDRESS A A 010—SELECT OVER-CURRENT
1
0
HIGH AND LOW REGISTER (SOCHLR_S)
0
1
55
40
The SOCHLR_s register allows the MCU to configure the
output over-current low and high detection levels,
respectively. Each output “s” is independently selected for
configuration based on the state of the D12:D11 bits
(Table 10).
* “_s” refers to the output, which is selected through bits D12:D11;
refer to Table 10, page 23.
ADDRESS A A 011—CURRENT DETECTION TIME
1
0
AND OPEN LOAD REGISTER (CDTOLR)
Table 10. Output Selection
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before an output latches OFF. Each output is
independently selected for configuration based on A1A0,
A1 (D12)
A0 (D11)
HS_s
0
0
1
1
0
1
0
1
HS0
HS1
HS2
HS3
which are the state of the D12:D11 bits (refer to Table 10,
page 23).
Bits D1:D0 (OCLT1_s:OCLT0_s) allow the MCU to select
one of three over-current fault blanking times defined in
Table 13. Note that these timeouts apply only to the over-
current low detection levels. If the selected over-current high
level is reached, the device will latch off within 20μs.
Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2:D0
set the over-current low detection level to one of eight
possible levels, as shown in Table 11, page 23. Bit D3 sets
the over-current high detection level to one of two levels, as
outlined in Table 12, page 23.
Table 13. Over-current Low Detection Blanking Time
OCLT[1:0]_s*
Timing
00
01
10
11
155ms
Do not use
75ms
150μs
* “_s” refers to the output, which is selected through bits D12:D11;
refer to Table 10, page 23.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FREESCALE [ Freescale ]
