FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
D4:D0, are used to configure and control the outputs and
SERIAL INPUT COMMUNICATION
their protection features.
SPI communication is accomplished using 16-bit
Multiple messages can be transmitted in succession to
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0 (Table 8).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit. In some cases, output selection is
done with bits D12:D11. The next three bits, D10:D8, are
used to select the command register. The remaining five bits,
The 33874 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 9, page 22, summarizes the SI registers.
Table 8. SI Message Bit Assignment
Bit Sig
SI Msg Bit
Message Bit Description
MSB
D15
D14:D15
D12:D11
D10:D8
D7:D5
D4:D1
D0
Watchdog in: toggled to satisfy watchdog requirements.
Not used.
Register address bits used in some cases for output selection.
Register address bits.
Not used.
Used to configure the inputs, outputs, and the device protection features and SO status content.
Used to configure the inputs, outputs, and the device protection features and SO status content.
LSB
Table 9. Serial Input Address and Configuration Bit Map
SI Data
D4
SI Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D3
D2
D1
D0
STATR_s WDIN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
X
0
0
0
1
1
0
0
0
1
X
0
1
1
0
1
0
1
1
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOA4
SOA3
SOA2
SOA1
SOA0
OCR0
OCR1
WDIN
WDIN
0
0
0
0
0
0
0
0
0
IN3_SPI
IN2_SPI
IN1_SPI
IN0_SPI
CSNS3 EN
SOCH_s
OL_DIS_s
CSNS2 EN
SOCL2_s
OCL_DIS_s
CSNS1 EN CSNS0 EN
SOCHLR_s WDIN
CDTOLR_s WDIN
A1 A0
A1 A0
A1 A0
SOCL1_s
OCLT1_s
SOCL0_s
OCLT0_s
A/O_s
DICR_s
UOVR
WDR
WDIN
WDIN
WDIN
WDIN
0
FAST_SR_s CSNS_high_s DIR_DIS_s
0
0
0
X
0
1
0
X
OT_latch-1
OT_latch_3
OT_latch_0
OT_latch_2
UV_DIS
WD1
OV_DIS
WD0
NAR
No Action (Allow Toggling of D15-WDIN)
RESET
0
0
0
0
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 10.
D15 is used to toggle watchdog event (WDIN)
DEVICE REGISTER ADDRESSING
ADDRESS 00000—STATUS REGISTER (STATR_S)
The following section describes the possible register
addresses and their impact on device operation.
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the OCR0, OCR1, SOCHLR,
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FREESCALE [ Freescale ]
