ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 18V, -40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OCTAL SERIAL DRIVERS (OUT1 - OUT8) (CONTINUED)
Output Off Open Circuit Fault Filter Timer(11)
Output Slew Rate
tOC
400
500
650
µs
V/µs
R
= 51Ω
= 51Ω
tSR(RISE)
tSR(FALL)
1.0
1.0
5.0
5.0
10
10
LOAD
LOAD
R
P1 Input Propagation Delay
µs
µs
Input @ 50% VDD to Output voltage 10% of final value
Input @ 50% VDD to Output voltage 90% of initial value
t(RISEDELAY)
t(FALLDELAY)
6.0
6.0
P3, P5, P7 Input Propagation Delay
Input @ 50% VDD to Output voltage 10% of final value
Input @ 50% VDD to Output voltage 90% of initial value
t(RISEDELAY)
t(FALLDELAY)
5.0
5.0
OSCILLATOR AND TIMER ACCURACY
Calibrated Timer Accuracy(11)
tTIMER
tTIMER
–
–
–
–
±10
±80
%
%
Un-calibrated Timer Accuracy
SPI DIGITAL INTERFACE TIMING (SO, SI, CS, SCLK)(12)
Required Low State Duration on VPWR for Reset(13)
t
µs
RESET
tLEAD
tLAG
VPWR ≤ 0.2V
1.0
–
–
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
ns
ns
ns
ns
100
50
–
–
–
–
–
–
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
SI to Rising Edge of SCLK
Required Setup Time
tSI(SU)
16
Rising Edge of SCLK to SI
Required Hold Time
tSI(HOLD)
20
–
–
5.0
5.0
–
–
SI, CS, SCLK Signal Rise Time(14)
tR(SI)
tF(SI)
–
ns
ns
ns
ns
ns
µs
SI, CS, SCLK Signal Fall Time(14)
–
–
Time from Falling Edge of CS to SO Low-impedance(15)
Time from Rising Edge of CS to SO High-impedance(16)
Time from Falling Edge of SCLK to SO Data Valid(17)
tSO(EN)
tSO(DIS)
tVALID
tSTR
–
150
150
150
1.0
–
–
–
25
Sequential Transfer Rate
Time required between data transfers
Notes
11. Assumes oscillator has been calibrated using SPI Calibrate Command
12. These parameters are guaranteed by design. Production test equipment uses 1MHz, 5.0V SPI interface.
13. This parameter is guaranteed by design, however it is not production tested.
14. Rise and Fall time of incoming SI, CS, and SCLK signals for design consideration to prevent the occurrence of double pulsing.
15. Time required for valid output status data to be available on SO pin.
16. Time required for output states data to be terminated at SO pin.
17. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FREESCALE [ Freescale ]
