FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Power On Reset (POR). All internal registers will be placed in
the reset state. The device has an Internal 100 kΩ resistor
pull down on the ENABLE pin.
operate. For applications where measurements are not
critical, the VCAL pin may grounded and an internally
generated reference will be used. Using the internally
generated reference will add ±10% to all tolerances in the
parametric table.
PULSE WIDTH MODULATION (PWM)
The PWM pins are control input pins for the MOSFET pre-
drivers. The PWM pins provide parallel control and can be
programmed for an OR function with the SPI bit or an AND
function with the SPI bit (See Table 12, on page 25 for SPI
message detail). Each PWM input pin has an internal 15µA
pull down current source. The current sources are active
when the device is in Normal Mode.
LOAD RESISTANCE FEEDBACK (LRFDBK)
The LRFDBK pin is an operational amplifier output. The
amplifier output voltage is proportional to the load resistance
for the selected channel. The channel is selected via the SPI.
DEFAULT
The DEFAULT input controls the operation of each driver
to a Default Mode. The DEFAULT input must be logic 0 for full
function of all output drivers. For more information on the
DEFAULT operation (See Functional Device Operation on
page 19).
DRAIN VOLTAGE SENSE (VDSNSX)
The VDSNSx pin has multiple functions for control and
diagnostics of the external MOSFET:
1. By monitoring the drain voltage of the external device,
short circuits and open circuits are detected. The filter
timer and threshold voltage are easily programmed
through SPI (see Table 10, on page 23 and Table 11,
on page 24 for SPI messages).
With the DEFAULT pin HIGH, the device is placed in
Default Mode. The DEFAULT pin is pulled up to the VDD
supply through an active pull up current source. In Default
Mode the device operates in the following manner:
1. OSS outputs are disabled.
2. The VDSNSx pins are use to determine the external
load resistance. Further information is provided in the
Device Operation section of this specification.
2. CCD1 and CCD2 outputs are disabled.
3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)
outputs and on board PWM controllers are disabled. PWMx
input control is enabled.
3. The VDSNSx pins provide a drain to gate clamp for
fast turn off of inductive loads and MOSFET protection.
In the Default Mode the device retains all register
GATE DRIVER OUTPUTS (GDX)
information and output status information. Normal operation
will resume when the DEFAULT pin transitions low again and
the device will operate as programmed prior to Default Mode.
The GDX pins are the gate drive outputs for an external
MOSFETS. Internal to the device is a Gate to Source resistor
designed to hold the external MOSFET in the OFF state while
the device is in POR.
RESISTOR EXTERNAL REFERENCE (REXT)
The reference current is used in the equation to calculate
the load resistance of the PWM outputs. The load resistance
measurement current is inversely proportional to REXT
current. The resistor value may be changed to adjust the load
measurement current. A 24Ω resistor to ground sets the
LRFDBK output to 260mV/Ω.
INPUTS (P1, P3, P5, P7)
The input pins for octal serial switch outputs 1,3,5,7. Each
input control pin has an internal pull down current source.
Two outputs may be controlled in parallel using the PX pins
(See Functional Device Operation on page 25).
EXPOSED PAD
VOLTAGE CALIBRATED INPUT (VCAL)
The silicon die is epoxy attached to the top side of the pad.
Although the device does not use the pad for electrical
conduction, the bottom side exposed pad of the package
should be grounded.
The Voltage calibrated input (VCAL) provides the IC with
a reference voltage for analog circuits. VCAL (EXT or INT)
must be applied for the CCD1 and CCD2 constant current
controllers and Load Resistance measurement function to
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FREESCALE [ Freescale ]
