PIN CONNECTIONS
48
47
46
45
44
43
42
41
40
39
38
37
NC
NC
NC
NC
GND
GND
GND
GND
NC
NC
NC
NC
NC
SCLK
MISO
MOSI
CS
WDOG
RXD
TXD
VDD
RST
INT
NC
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
NC
CANL
CANH
L3
L2
L1
L0
HS
VSUP
V2 CTRL
V2
NC
Figure 4. 33742 48-Pin Connections
Table 3. 33742 48-Pin Definitions
A functional description of each pin can be found in the
section beginning on page
Pin
1, 12-16,
21-25,
36-40,
45-48
2
3
4
5
6
7
8
9
10
11
17-20
41-44
Pin Name
NC
Formal Name
No Connect
No connection.
Definition
SCLK
MISO
MOSI
CS
WDOG
Serial Data Clock
Master In Slave Out
Master Out Slave In
Chip Select
(Active LOW)
Watchdog Output
(Active LOW)
Receive Data
Transmit Data
Voltage Digital Drain
Reset Output
(Active LOW)
Interrupt Output
(Active LOW)
Ground
RXD
TXD
VDD
RST
INT
GND
NC
NC
NC
NC
GND
GND
GND
GND
NC
NC
NC
NC
Clock input pin for the Serial Peripheral Interface (SPI).
SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-
impedance state.
SPI data received by the 33742.
The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted
LOW, the 33742 is the selected device of the SPI bus.
The WDOG output pin is asserted LOW if the software watchdog is not correctly
triggered.
CAN bus receive data output pin.
CAN bus transmit data input pin.
5.0 V regulator output pin. Supply pin for the MCU.
This is the device reset output pin whose main function is to reset the MCU. This pin has
an internal pullup current source to VDD.
This output is asserted LOW when an enabled interrupt condition occurs. The output is
a push-pull structure.
These device ground pins are internally connected to the package lead frame to provide
a 33742-to-PCB thermal path.
13
14
15
16
17
18
19
20
21
22
23
24
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
