Document Revision History
Table 68. Document Revision History (continued)
Substantive Change(s)
Rev.
Date
Number
3
11/2006
• Updated note in introduction.
• In the features list in Section 1, “Overview,” updated DDR data rate to show 400 MHz for DDR2
for TBGA parts for silicon 3.x and 400 MHz for DDR2 for TBGA parts for silicon 3.x.
• In Section 23, “Ordering Information,” replicated note from document introduction.
2
8/2006
• Changed all references to revision 2.0 silicon to revision 3.0 silicon.
• Changed VIH minimum value in Table 40, “JTAG Interface DC Electrical Characteristics,” to
OVDD – 0.3.
• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
• In Table 66, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
1
4/2006
• Removed Table 20, “Timing Parameters for DDR2-400.”
• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
• Changed Min and Max values for VIH and VIL in Table 40Table 44,“PCI DC Electrical
Characteristics.”
• In Table 55, “MPC8349EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
• Table 55, “MPC8349EA (TBGA) Pinout Listing,” in row AVDD3 changed power supply from
“AVDD3” to ‘—.’
0
3/2006
Initial public release
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
86
FREESCALE [ Freescale ]
