Document Revision History
Table 68. Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
9
2/2009
• Added footnote 6 to Table 7.
• In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.
• In Table 39, corrected tLBKHOV parameter to tLBKLOV (output data is driven on falling edge of clock
in DLL bypass mode). Similarly, made the same correction to Figure 22, Figure 24, and Figure 25
for output signals.
• Added footnote 11 to Table 55.
• Added footnote 4 to Table 66.
• In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
• In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”
• In Table 57, corrected the max csb_clk to 266 MHz.
• In Table 62, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz
• In Table 66, updated note 1 to say the following: “For temperature range = C, processor frequency
is limited to 533 with a platform frequency of 266.”
8
7
4/2007
3/2007
• In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and
added USB to the seventh row.
• In Section 21.7, “Pull-Up Resistor Requirements,“deleted last two paragraphs and after first
paragraph, added a new paragraph.
• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
• In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (csb_clk)’
row, changed the value in the 533 MHz column to 100-333.
• In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK
Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz
CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306,
changed the CORE PLL value to 0000110.
• In Section 23, “Ordering Information,” replaced first paragraph and added a note.
• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
6
5
2/2007
1/2007
• Page 1, updated first paragraph to reflect PowerQUICC II Pro information.
• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to tCISKEW
and deleted original note 3; renumbered the remaining notes.
• In Figure 41, “JTAG Interface Connection,” updated with new figure.
• In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced third sentence of
first paragraph directing customer to product summary page for available frequency configuration
parts.
• In Table 1, “Absolute Maximum Ratings,” added (1.36 max for 667-MHz core frequency) to max
VDD and AvDD values.
• In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply
voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
• In Table 4, “MPC8349EA Power Dissipation,” added two footnotes to 667-MHz row showing
nominal core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
• In Table 54, “MPC83479EA (TBGA) Pinout Listing,” updated VDD nd AVDD rows to show nominal
core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.
4
12/2006
Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified Tddkhds for 333 MHz
from 900 ps to 775 ps.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
85
FREESCALE [ Freescale ]
