FUNCTIONAL DEVICE OPERATION
SUPPLIES
SW1 PWM Pulse Skipping mo de Efficiency Vo ut = 0,725 V
SW1 PWM Pu lse Skip ping mo de Efficiency Vo ut = 0,725 V
100 %
90 %
100 %
90 %
80 %
80 %
70 %
70 %
60 %
50 %
40 %
60 %
Vin
Vin
Vin
=
=
=
3,0 00
3,6 00
4,6 50
V
V
V
Vin = 3 ,00 0 V
Vin = 3 ,60 0 V
Vin = 4 ,65 0 V
50 %
40 %
30 %
30 %
20 %
10 %
0 %
20 %
10 %
0 %
0
50 1 00 150 200 25 0 300 35 0 4 00 450 50 0 55 0 6 00 650 70 0 7 50 800 85 0 90 0 9 50 10 0 1 05
0
1 0
20
3 0
40
50
60
70
80
90
10 0
0
0
Ilo a d (mA)
Il oa d (mA)
SW2 PWM Pu lse Skip ping mo de Efficiency Vo ut = 1.250 V
SW2 PWM Pu lse Skip pin g mod e Efficiency Vou t = 1.250
V
100 %
100 %
90 %
80 %
90 %
80 %
70 %
60 %
70 %
60 %
50 %
40 %
30 %
20 %
Vin = 3 ,00 0 V
Vin = 3 ,60 0 V
Vin = 4 ,65 0 V
Vin
Vin
Vin
=
3, 000
3, 600
4, 650
V
50 %
40 %
30 %
20 %
=
=
V
V
10 %
0 %
10 %
0 %
0
1 0
20
3 0
40
50
60
70
80
90
10 0
0
50 1 00 1 50 20 0 25 0 300 350 4 00 4 50 50 0 55 0 600 650 7 00 7 50 80 0 85 0 900
Ilo a d (mA)
Iloa d (mA)
SW4 PWM Pu lse Skip ping mo de Efficiency Vo ut = 1.800 V
SW4 PWM Pulse Skipping mo de Efficiency Vo ut = 1.800 V
100 %
100 %
90 %
80 %
90 %
80 %
70 %
60 %
50 %
40 %
70 %
60 %
50 %
40 %
Vin = 3 ,00 0 V
Vin = 3 ,60 0 V
Vin = 4 ,65 0 V
Vin
Vin
Vin
=
3,0 00
3,6 00
4,6 50
V
=
=
V
V
30 %
20 %
10 %
0 %
30 %
20 %
10 %
0 %
0
1 0
20
3 0
40
50
60
70
80
90
10 0
0
50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00
Ilo a d (mA)
Il oa d (mA)
Figure 19. Buck Switcher PWM (Pulse Skipping) Efficiency
DYNAMIC VOLTAGE SCALING
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the
processor. SW1 and SW2 allow for three different set points with controlled transitions to avoid sudden output voltage changes,
which could cause logic disruptions on their loads. Preset operating points for SW1 and SW2 can be set up for:
• Normal operation: output value selected by SPI bits SWx[4:0]. Voltage transitions initiated by SPI writes to SWx[4:0] are
governed by the same DVS stepping rate that is programmed for DVSx pin initiated transitions.
• DVS: output can be higher or lower than normal operation for tailoring to application requirements. Configured by SPI bits
SWxDVS[4:0] and controlled by a DVSx pin transition.
• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention
voltage of a given process. Set by SPI bits SWxSTBY[4:0] and controlled by a Standby event (STANDBY logically and'd with
STANDBYSEC). Voltage transitions initiated by Standby are governed by the same DVS stepping that is programmed for
DVSx pin initiated transitions.
The following tables summarize the set point control and DVS time stepping applied to SW1 and SW2.
Table 49. DVS Control Logic Table for SW1 and SW2
STANDBY (60)
DVSx Pin
Set Point Selected by
0
0
1
0
1
X
SWx[4:0]
SWxDVS[4:0]
SWxSTBY[4:0]
Notes
60. STANDBY is the logical anding of STANDBY and STANDBYSEC
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
78
FREESCALE [ Freescale ]
