FUNCTIONAL DEVICE OPERATION
OPERATING MODES
Any peripheral loading on SW4 should be isolated from the SW4 output node by the PWGT2 switch, which opens in both low
power off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the memory
subsystem.
Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and an the MEMHLDI interrupt
bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since
software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.
No specific timer is running in this mode.
Buck switchers that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when
coming out of MEMHOLD and entering a Warm Boot. The switchers will be reconfigured for their default settings as selected by
the PUMS pin in the normal time slot that would affect them.
User Off
RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled. CLK32KMCU
(connected to the processor's CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set,
or if DRM is set.
The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1, and/or SW2, and/or SW3 supply domains
can be configured for SWxUOMODE = 1 to keep them powered through the User Off event. If one of the switchers can be shut
down on in User Off, its mode bits would typically be set to 0.
Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens
in both Low Power Off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining
the processor core.
Since power is maintained for the core (which is put into its lowest power state) and since MCU RESETBMCU does not trip,
the processor's state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be
used for very low frequency / low power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where
the system left off before the USEROFF command.
Upon a turn on event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off
will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with
external memory. No specific timer is running in this mode.
Warm Start
Entered upon a Turn On event from User Off. The switchers and regulators are powered up sequentially to limit the inrush
current; see the Power Up section for sequencing and default level details. If SW1, SW2, SW3, and/or SW4 were configured to
stay on in User Off mode, they will not be turned off when coming out of User Off and entering a Warm Start. The buck switchers
will be reconfigured for their default settings as selected by the PUMS pin in the respective time slot defined in the sequencer
selection.
RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if enabled via the SPI. The reset timer starts
running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is
generated, and RESETB will go high.
Internal MemHold Power Cut
Refer to the next section for details about Power Cuts and the associated state machine response.
POWER CUT DESCRIPTION
When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold
Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well
as the on chip memory registers and some other power control related bits. All other supplies will be disabled.
The maximum duration of a power cut is determined by the PCUT timer PCT[7:0] preset via SPI. When a PCUT occurs, the
PCUT timer will internally be decremented till it expires, meaning counted down to zero. The contents of PCT[7:0] does not reflect
the actual count down value but will keep the programmed value and therefore does not have to be reprogrammed after each
power cut.
If power is not reestablished above BPON before the PCUT timer expires, the state machine transitions to the Off mode at
expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT.
Upon re-application of power before expiration (an “successful PCUT”, defined as BP first rising above the UVDET threshold
and then above the BPON threshold before the PCUT timer expires), a Cold Start is engaged.
13892
Analog Integrated Circuit Device Data
58
Freescale Semiconductor
FREESCALE [ Freescale ]
