FUNCTIONAL DEVICE OPERATION
OPERATING MODES
GLOBAL SYSTEM RESTART
A global system restart can be enabled by clearing the GLBRSTENB bit. If this bit is cleared, a 12 second press to the
PWRON3 button will reset the system and the following actions will take place:
• - Power down
• - Disable the charger
• - Reset the registers all the registers including the RTCPORB registers
• - Power back up after the difference between the 12 sec timer, and when the user releases the button as the power off time
(for example, if the power button was held for 12.1 s, then the time that the IC would be off would be only 100 mS)
If PWRON3 is held low for less than 12 seconds, it will act as a normal PWRON pin. This feature is enabled by default in the
13892A, and disabled by default in 13892B.
CLK32KMCU CLOCK DRIVER CONTROL THROUGH STATES
As described previously, the clocking behavior is influenced by the state machine is in and the setting of the clocking related
SPI bits. A summary is given in Table 23 for the clock output CLK32KMCU.
Table 23. CLK32MCU Control Logic Table
Mode
DRM
CLK32KMCUEN
USEROFFCLK
Clock Output CLK32KMCU
0
1
0
1
0
0
1
0
X
X
0
X
X
X
X
X
0
Disabled
Enabled
Disabled
Enabled
Enabled
Disabled
Off, Memory Hold, Internal MEMHOLD PCUT
On, Cold Start, Warm Start, Watchdog, User Off Wait
User Off
X
1
X
X
1
X
1
Enabled
TURN ON EVENTS
When in Off mode, the MC13892 can be powered on via a Turn On event. The Turn On events are listed in Table 24. To
indicate to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On
events. Masking the interrupts related to the turn on events will not prevent the part to turn on, except for the time of day alarm.
Power Button Press
PWRON1, PWRON2, or PWRON3 pulled low with corresponding interrupts and sense bits PWRON1I, PWRON2I, or
PWRON3I, and PWRON1S, PWRON2S, or PWRON3S. A power on/off button is connected here. The PWRONx can be
hardware debounced through a programmable debouncer PWRONxDBNC[1:0] to avoid the application to power up upon a very
short key press. In addition, a software debounce can be applied. BP should be above UVDET. The PWRONxI interrupt is
generated for both the falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both
falling and rising edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following
table. The PWRONxI interrupt is cleared by software or when cycling through the Off mode.
Table 24. PWRONx Hardware Debounce Bit Settings
Bits
State
Turn On Debounce (ms)
Falling Edge INT Debounce (ms)
Rising Edge INT Debounce (ms)
00
01
10
11
0
31.25
31.25
125
31.25
31.25
31.25
31.25
31.25
125
PWRONxDBNC[1:0]
750
750
Notes
36. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
60
FREESCALE [ Freescale ]
