FUNCTIONAL DEVICE OPERATION
POWER CONTROL SYSTEM
POWER CONTROL SYSTEM
INTERFACE
The power control system on the MC13892 interfaces with the processor via different IO signals and the SPI/I2C bus. It also
uses on chip signals and detector outputs. Table 22 gives a listing of the principal elements of this interface.
Table 22. Power Control System Interface Signals
Name
PWRON1
Type of Signal
Function
Input pin
Input pin
Input pin
SPI bits
SPI bits
SPI bits
SPI bits
SPI bit
Power on/off 1 button connection
Power on/off 2 button connection
Power on/off 3 button connection
PWRONx pin interrupt /mask / sense bits
PWRON2
PWRON3
PWRONxI/M/S
PWRON1DBNC[1:0]
PWRON2DBNC[1:0]
PWRON3DBNC[1:0]
PWRON1RSTEN
PWRON2RSTEN
PWRON3RSTEN
RESTARTEN
SYSRSTI/M
WDI
Sets time for the PWRON1 pin hardware debounce
Sets time for the PWRON2 pin hardware debounce
Sets time for the PWRON3 pin hardware debounce
Allows for system reset through the PWRON1 pin
Allows for system reset through the PWRON2 pin
Allows for system reset through the PWRON3 pin
Allows for system restart after a PWRON initiated system reset
PWRONx System restart interrupt / mask bits
SPI bit
SPI bit
SPI bit
SPI bits
Input pin
SPI bit
Watchdog input has to be kept high by the processor to keep the MC13892 active
Allows for system restart through the WDI pin
WDIRESET
WDIRESETI/M
RESET
SPI bits
Output pin
Output pin
Input pin
Input pin
Input pin
SPI bit
WDI System restart interrupt / mask bits
Reset Bar output (active low) to the application. Requires an external pull-up
Reset Bar output (active low) to the processor core. Requires an external pull-up
Switchers and regulators power up sequence and defaults selection 1
Switchers and regulators power up sequence and defaults selection 2
Signal from primary processor to put the MC13892 in a low power mode
Standby signal polarity setting
RESETMCU
PUMS1
PUMS2
STANDBY
STANDBYINV
STANDBYSEC
STANDBYSECINV
STBYDLY[1:0]
BPON
Input pin
SPI bit
Signal from secondary processor to put the MC13892 in a low power mode
Secondary standby signal polarity setting
SPI bits
Threshold
SPI bits
Threshold
SPI bits
Threshold
SPI bits
SPI bits
Threshold
Input pin
Output pin
Output pin
SPI bit
Sets delay before entering standby mode
Threshold validating turn on events
BPONI/M/S
LOBATH
BP turn on threshold interrupt / mask / sense bits
Threshold for a low battery warning
LOBATHI/M/S
LOBATL
Low battery warning interrupt / mask / sense bits
Threshold for a low battery detect
LOBATLI/M/S
BPSNS [1:0]
UVDET
Low battery detect interrupt / mask / sense bits
Selects for different settings of LOBATL and LOBATH thresholds
Threshold for under-voltage detection, will shut down the device
Connection for Lithium based coin cell
LICELL
CLK32KMCU
CLK32K
Low frequency system clock output for the processor 32.768 kHz
Low frequency system clock output for application (peripherals) 32.768 kHz
Enables the CLK32KMCU clock output
CLK32KMCUEN
Keeps VSRTC and CLK32KMCU active in all states for digital rights management, including off
mode
DRM
SPI bit
PCEN
SPI bit
SPI bits
SPI bits
SPI bit
Enables power cut support
PCI/M
Power cut detect interrupt / mask bits
Allowed power cut duration
PCT[7:0]
PCCOUNTEN
PCCOUNT[3:0]
PCMAXCNT[3:0]
PCUTEXPB
Enables power cut counter
SPI bits
SPI bits
SPI bit
Power cut counter
Maximum number of allowed power cuts
Indicates a power cut timer counter expired
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
55
FREESCALE [ Freescale ]
