FUNCTIONAL DEVICE OPERATION
I2C INTERFACE
INTERRUPT HANDLING
CONTROL
The MC13892 has interrupt generation capability to inform the system on important events occurring. An interrupt is signaled
to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I2C.
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each
interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line
to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,
the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked except the USB Low power boot, so the
processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the
interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources.
They are read only, and not latched or clearable.
Interrupts generated by external events are debounced, meaning that the event needs to be stable throughout the debounce
period before an interrupt is generated.
BIT SUMMARY
Table 12 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral
descriptions, refer to the related chapters.
Table 12. Interrupt, Mask and Sense Bits
DebounceTi
me
Interrupt
Mask
Sense
Purpose
Trigger
Section
ADC has finished requested
conversions
ADCDONEI
ADCDONEM
-
L2H
0
page 99
ADCBIS has finished requested
conversions
ADCBISDONEI
TSI
ADCBISDONEM
TSM
-
-
L2H
0
page 99
page 99
Touch screen wake-up
Dual
30ms
CHGDETS
Charger detection sense is 1 if
detected
32 ms
CHGDETI
CHGDETM
Dual
page 88
CHGENS
USBOVS
Charger state sense is 1 if active
100 ms
VBUS over-voltage
Sense is 1 if above threshold
USBOVI
USBOVM
Dual
60 μs
page 88
CHGREVI
CHGREVM
-
-
Charger path reverse current
Charger path short circuit
L2H
L2H
1.0 ms
1.0 ms
page 88
page 88
CHGSHORTI
CHGSHORTM
Charger fault detection
00 = Cleared, no fault
01 = Charge source fault
10 = Battery fault
CHGFAULTI
CHGFAULTM
CHGFAULTS[1:0]
L2H
10 ms
page 88
11 = Battery temperature
Charge current below threshold
Sense is 1 if above threshold
CHGCURRI
CCCVI
CHGCURRM
CCCVM
CHGCURRS
CCCVS
H2L
Dual
L2H
1.0 ms
100 ms
30 ms
page 88
page 88
page 55
CCCVI transition detection
BP turn on threshold detection.
Sense is 1 if above threshold.
BPONI
BPONM
BPONS
Low battery detect
Sense is 1 if below LOBATL
threshold
LOBATLI
BVALIDI
LOBATLM
BVALIDM
LOBATLS
BVALIDS
L2H
0
page 55
L2H: 20-
24 ms
H2L: 8-
12 ms
USB B-session valid
Dual
page 110
Sense is 1 if above threshold
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
47
FREESCALE [ Freescale ]
