FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
Table 10. SPI Interface Timing Specifications
Parameter
Description
T min (ns)
15
TSELSU
TSELHLD
TSELLOW
TCLKPER
TCLKHIGH
TCLKLOW
TWRTSU
TWRTHLD
TRDSU
Time CS has to be high before the first rising edge of CLK
Time CS has to remain high after the last falling edge of CLK
Time CS has to remain low between two transfers
15
15
Clock period of CLK
38
Part of the clock period where CLK has to remain high
Part of the clock period where CLK has to remain low
Time MOSI has to be stable before the next rising edge of CLK
Time MOSI has to remain stable after the rising edge of CLK
Time MISO will be stable before the next rising edge of CLK
Time MISO will remain stable after the falling edge of CLK
Time MISO needs to become active after the rising edge of CS
Time MISO needs to become inactive after the falling edge of CS
15
15
4.0
4.0
4.0
4.0
4.0
4.0
TRDHLD
TRDEN
TRDDIS
Notes
34. This table reflects a maximum SPI clock frequency of 26 MHz
Table 11. SPI Interface Logic IO Specifications
Parameter
Condition
Min
Typ
Max
0.3*SPIVCC
SPIVCC+0.3
0.2
Units
Input Low CS, MOSI, CLK
Input High CS, MOSI, CLK
Output Low MISO, INT
Output High MISO, INT
SPIVCC Operating Range
0
0.7*SPIVCC
0
-
-
-
-
-
V
V
V
V
V
Output sink 100 μA
Output source 100 μA
SPIVCC-0.2
1.75
SPIVCC
3.1
CL = 50 pF, SPIVCC = 1.8 V
SPIDRV[1:0] = 00 (default)
SPIDRV[1:0] = 01
-
-
-
-
11
6.0
-
-
-
-
ns
ns
ns
ns
MISO Rise and Fall Time
SPIDRV[1:0] = 10
High Z
22
SPIDRV[1:0] = 11
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
FREESCALE [ Freescale ]
