FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
Table 8. Register Set
Register
Register
Register
Register
Test 1
12
13
14
15
Unused
28
29
30
31
Switchers 4
44
45
46
47
ADC 1
ADC 2
ADC 3
ADC4
60
61
62
63
Power Control 0
Power Control 1
Power Control 2
Switchers 5
Test 2
Test 3
Test 4
Regulator Setting 0
Regulator Setting 1
The SPI interface is comprised of the package pins listed in Table 9.
Table 9. SPI Interface Pin Description
SPI Bus
CLK
Description
Clock input line, data shifting occurs at the rising edge
MOSI
MISO
CS
Serial data input line
Serial data output line
Clock enable line, active high
Interrupt
INT
Supply
SPIVCC
Description
Description
Interrupt to processor
Processor SPI bus supply
SPI INTERFACE DESCRIPTION
The control bits are organized into 64 fields. Each of these 64 fields contains 32 bits. A maximum of 24 data bits are used per
field. In addition, there is one “dead” bit between the data and address fields. The remaining bits include 6 address bits to address
the 64 data fields and one write enable bit to select whether the SPI transaction is a read or a write.
The register set will be to a large extent compatible with the MC13783 in order to facilitate software development.
For each SPI transfer, first a one is written to the read/write bit if this SPI transfer is to be a write. A zero is written to the read/
write bit if this is to be a read command only.
The CS line must remain high during the entire SPI transfer. To start a new SPI transfer, the CS line must go inactive and then
go active again. The MISO line will be tri-stated while CS is low.
To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded at the beginning of the
SPI sequence.
Figure 5. SPI Transfer Protocol Single Read/Write Access
13892
Analog Integrated Circuit Device Data
42
Freescale Semiconductor
FREESCALE [ Freescale ]
