F81866A
Extended Control Register ⎯ Base + 402h
Bit
Name
R/W Default
Description
000: SPP Mode.
001: PS/2 Parallel Port Mode.
010: Parallel Port Data FIFO Mode.
011: ECP Parallel Port Mode.
7-5
ECP_MODE
R/W
000 100: EPP Mode.
101: Reserved.
110: Test Mode.
111: Configuration Mode.
Only valid in ECP.
0: disable the interrupt generated on the falling edge of ERR#.
1: enable the interrupt generated on the falling edge of ERR#.
4
3
ERRINTR_EN
DAMEN
R/W
R/W
0
0
0: disable DMA.
1: enable DMA. DMA starts when SERVICEINTR is 0.
0: enable the following case of interrupt.
DMAEN = 1: DMA mode.
DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more
bytes are free in the FIFO.
2
SERVICEINTR
R/W
1
DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more
bytes are valid to be read in the FIFO.
0: The FIFO has at least 1 free byte.
1: The FIFO is completely full.
1
0
FIFOFULL
R
R
0
0
0: The FIFO contains at least 1 byte.
1: The FIFO is completely empty.
FIFOEMPTY
6.4 Hardware Monitor
6.4.1General Description
6.4.1.1Voltage
For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.048V.
Therefore the voltage under 2.048V (ex:1.5V) can be directly connected to these analog inputs. The
voltage higher than 2.048V should be reduced by a factor with external resistors so as to obtain the
input range. Only 3Vcc is an exception for it is main power of the F81866A. Therefore 3Vcc can
directly connect to this chip’s power pin and need no external resistors. There are two functions in
this pin with 3.3V. The first function is to supply internal analog power of the F81866A and the second
function is that voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage.
The internal serial resistors are two 150KΩ, so that the internal reduced voltage is half of +3.3V (See
figure 6-1).
There are four voltage inputs in the F81866A and the voltage divided formula is shown as follows:
32
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
