F81866A
6.3 Parallel Port
The parallel port in F81866A supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel
port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities Parallel Port ( ECP ) mode. Refer to the
configuration registers for more information on selecting the mode of operation.
The below content is about the Parallel Port device register descriptions. All the registers are for software
porting reference.
Parallel Port Data Register ⎯ Base + 0
Bit
Name
R/W Default
Description
7-0
DATA
R/W 00h The output data to drive the parallel port data lines.
ECP Address FIFO Register ⎯ Base + 0
Bit
Name
R/W Default
Description
Access only in ECP Parallel Port Mode and the ECP_MODE programmed in
the Extended Control Register is 011.
The data written to this register is placed in the FIFO and tagged as an
Address/RLE. It is auto transmitted by the hardware. The operation is only
defined for forward direction. It divide into two parts :
7-0
ECP_AFIFO
R/W
00h
Bit 7 :
0: bits 6-0 are run length, indicating how many times the next byte to appear (0
= 1time, 1 = 2times, 2 = 3times and so on).
1: bits 6-0 are ECP address.
Bit 6-0 : Address or RLE depends on bit 7.
Device Status Register ⎯ Base + 1
Bit
Name
R/W Default
Description
Inverted version of parallel port signal BUSY.
7
BUSY_N
R
R
R
R
R
R
-
-
Version of parallel port signal ACK#.
Version of parallel port signal PE.
Version of parallel port signal SLCT.
Version of parallel port signal ERR#.
Reserved. Return 11b when read.
6
5
ACK_N
PERROR
SELECT
ERR_N
-
4
-
3
-
2-1
Reserved
11
This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0: no time out error.
0
TMOUT
R
-
1: time out error occurred, write 1 to clear.
Device Control Register ⎯ Base + 2
Bit
Name
R/W Default
11
Description
7-6
Reserved
-
Reserved. Return 11b when read.
29
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
