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F81866AD-I 参数 Datasheet PDF下载

F81866AD-I图片预览
型号: F81866AD-I
PDF下载: 下载PDF文件 查看货源
内容描述: 6个UART超级IO 128字节FIFO和电源 [6 UARTs Super IO With 128 Bytes FIFO and Power]
分类和应用: 先进先出芯片
文件页数/大小: 210 页 / 1806 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F81866A  
0: the parallel port is in output mode.  
1: the parallel port is in input mode.  
It is auto reset to 1 when in SPP mode.  
5
DIR  
R/W  
0
4
3
ACKIRQ_EN  
SLIN  
R/W  
R/W  
0
0
Enable an interrupt at the rising edge of ACK#.  
Inverted and then drives the parallel port signal SLIN#.  
When read, the status of inverted SLIN# is return.  
Drives the parallel port signal INIT#.  
2
1
0
INIT_N  
AFD  
R/W  
R/W  
R/W  
0
0
0
When read, the status of INIT# is return.  
Inverted and then drives the parallel port signal AFD#.  
When read, the status of inverted AFD# is return.  
Inverted and then drives the parallel port signal STB#.  
When read, the status of inverted STB# is return.  
STB  
EPP Address Register Base + 3  
Bit  
Name  
R/W Default  
Description  
Write this register will cause the hardware to auto transmit the written data to  
the device with the EPP Address Write protocol.  
7-0  
EPP_ADDR  
R/W  
00h  
Read this register will cause the hardware to auto receive data from the device  
by with the EPP Address Read protocol.  
EPP Data Register Base + 4 – Base + 7  
Bit  
Name  
R/W Default  
Description  
Write this register will cause the hardware to auto transmit the written data to  
the device with the EPP Data Write protocol.  
7-0  
EPP_DATA  
R/W  
00h  
Read this register will cause the hardware to auto receive data from the device  
by with the EPP Data Read protocol.  
Parallel Port Data FIFO Base + 400h  
Bit  
Name  
R/W Default  
Description  
Data written to this FIFO is auto transmitted by the hardware to the device by  
using standard parallel port protocol.  
7-0  
C_FIFO  
R/W  
00h  
It is only valid in ECP and the ECP_MODE is 010b.The operation is only for  
forward direction.  
ECP Data FIFO Base + 400h  
Bit  
Name  
R/W Default  
Description  
Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to  
the device by using ECP parallel port protocol.  
Data is auto read from device into the FIFO when DIR is 1 by the hardware by  
using ECP parallel port protocol. Read the FIFO will return the content to the  
system.  
7-0  
ECP_DFIFO  
R/W  
00h  
It is only valid in ECP and the ECP_MODE is 011b.  
30  
Jan, 2012  
V0. 12P  
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