F81867
General purpose IO.
GPIO77
STB#
I/OOD12st, 5v
I/OOD12st,5v
An active low output is used to latch the parallel data
into the printer. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP
mode.
110
111
3VCC
3VCC
PWM3 Output where its frequency range is
183Hz~46.875KHz.
It
can
support
various
PWM3
OOD12st, 5v
applications such as manual fan control, and
backlight brightness control.
GPIO80
PD0
I/OOD12st, 5v
I/O12st,5v
General purpose IO. Support scan code function.
Parallel port data bus bit 0. Refer to the description of
the parallel port for the definition of this pin in ECP
and EPP mode.
General purpose IO. Support scan code function.
GPIO81
I/OOD12st, 5v
I/O12st,5v
112
113
114
115
116
117
118
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
Parallel port data bus bit 1.
PD1
GPIO82
I/OOD12st, 5v
I/O12st,5v
General purpose IO. Support scan code function.
Parallel port data bus bit 2.
PD2
GPIO83
I/OOD12st, 5v
I/O12st,5v
General purpose IO. Support scan code function.
Parallel port data bus bit 3.
PD3
General purpose IO. Support scan code function.
GPIO84
I/OOD12st, 5v
I/O12st,5v
Parallel port data bus bit 4.
PD4
GPIO85
I/OOD12st, 5v
I/O12st,5v
General purpose IO. Support scan code function.
Parallel port data bus bit 5.
PD5
GPIO86
I/OOD12st, 5v
I/O12st,5v
General purpose IO. Support scan code function.
Parallel port data bus bit 6.
PD6
GPIO87
I/OOD12st, 5v
I/O12st,5v
General purpose IO. Support scan code function.
Parallel port data bus bit 7.
PD7
5.6 Hardware Monitor
Pin
Pin Name
BEEP
Type
OD24t,5v
PWR
Description
Beep pin.
GPIO16
I/OOD12st,5v
General purpose IO.
71
I_VSB3V
I2C Interface DATA pin. AMD TSI & Intel PCH
(IBX Peak) data pin.
SDA
ILv/OD12st,5v
CIRRX#
PECI
INst,5v
Ilv /OD8, S1
I/OOD12st,5v
OD12,5v
CIR receiver input.
PECI interface pin.
72
75
I_VSB3V
GPIO17
OVT#
General purpose IO.
I_VSB3V Over temperature signal output.
Alert a signal when temperature over limit
ALERT#
GPIO20
SCL
OD12,5v
setting.
General purpose IO.
I/OOD24st,5v
ILv/OD24st,5v
76
85
I_VSB3V
I2C interface Clock. Clock output for AMD TSI &
Intel PCH (IBX Peak).
CIR receiver input.
CIRRX#
INst,5v
INst,5v
Case Open Detection #. This pin is connected to
COPEN#
VBAT
22
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
