F81867
5.2 Clock
Pin
Pin Name
Type
PWR
3VCC 33MHz PCI clock input.
System clock input. According to the input frequency
Description
32
PCICLK
INst
33
CLKIN
INst
3VCC
14.318/24/48MHz (default 48MHz).
5.3 LPC Interface
Pin
Pin Name
Type
PWR
3VCC
Description
Reset signal. It can connect to PCIRST# signal on
the host.
23
LRESET#
INst
24
25
LDRQ#
O16
3VCC Encoded DMA Request signal.
3VCC Serial IRQ input/Output.
SERIRQ
I/O16st
Indicates start of a new cycle or termination of a
26
LFRAME#
INst
3VCC
broken cycle.
These signal lines communicate address, control,
3VCC and data information over the LPC bus between a
host and a peripheral.
27-30
LAD[0:3]
I/O16st
32
33
PCICLK
CLKIN
INst
INst
3VCC 33MHz PCI clock input.
System clock input. According to the input frequency
3VCC
14.318/24/48MHz (default 48MHz).
5.4 FDC
Pin No.
Pin Name
Type
PWR
Description
General Purpose IO.
I/OOD14st, 5v
GPIO50
Drive Density Select.
OD14,5v
Set to 1 – High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
UART Request To Send. An active low signal informs
the modem or data set that the controller is ready to
send data.
DENSEL#
RTS6#
9
3VCC
O14
I/OOD14st, 5v
OD14,5v
General Purpose IO.
GPIO51
MOA#
Motor A On. When set to 0, this pin enables disk
10
3VCC drive 0. This is an open drain output.
UART Serial Input. Used to receive serial data
through the communication link.
INst,5v
I/OOD14st, 5v
OD14,5v
SIN6
GPIO52
General Purpose IO.
Drive Select A. When set to 0, this pin enables disk
3VCC drive A. This is an open drain output.
UART Serial Output. Used to transmit serial data
out to the communication link.
DRVA#
11
12
SOUT6
GPIO53
WDATA#
O14
I/OOD14st, 5v
OD14,5v
General Purpose IO.
3VCC
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD.
18
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
